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ABSTRACT
A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ is a three-transistor SRAM.
It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
Yes, the density vs power tradeoff could make a lot of sense in a few applications.
I wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.
Is the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
20% growth then 20% again still seems pretty good to me though. I guess compounded that is a 44% increase N3 to A14 which also starts to look much better if you zoom out a bit. I mean 44% more density since a few years ago seems, if not massive, not insignificant, like you will definitely notice it.
Come on we're in the 21st century, UTF-8 is pervasive. Just call it "Å14" node.
I don't think it's a UTF-8 problem. It's just that most people don't have "Å" on their keyboard.
TSMC: https://www.tsmc.com/english/dedicatedFoundry/technology/log...
Not sure what this source is, but it looks sketchy.
The source is the IEDM conference website where TSMC will be presenting the paper in Dec 2026
IEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
Sorry, I got thrown off by the domain.