- 80comments
- 6comments
- 124comments
- 52comments
- 34comments
- 595comments
- 139comments
- 12comments
- 237comments
- 84comments
- 170comments
- 73comments
- 6comments
- 234comments
- 42comments
- —discuss
- 4comments
- 121comments
- 3comments
- 159comments
- 13comments
- 25comments
- 62comments
- 29comments
- 45comments
- —discuss
- 374comments
- 40comments
- 120comments
- 49comments
For some reason I thought the reason that this hadn't been implemented already was that Sony had patents on multithreaded binary translation. I guess those might have only applied to specific techniques for heterogeneous or ring-bus systems (i.e. Cell), though.
No, it's just that it's the kind of feature that's quite hard to retrofit to an existing design, since it breaks existing assumptions in a lot of places. And it's only relatively recently that the kind of embedded board that you usually want to emulate with QEMU has had a multi-core CPU.
This has recently landed in upstream qemu and will be available with the 2.9 release.
Some bugs are being found that affect single-vCPU emulation. There's still a possibility that it will be reverted before the release.
does this mean one could run (without hardware support, say in aws) smp virtualization? i.e. linux on linux or windows on linux (why not just spawn another machine? because you want to have more control than what aws provides)
This allows you to create one host thread per guest vcpu, so yes, you can run a smp guest on aws. But, it will be pretty slow compared to KVM, since the execution of the threads is limited by the host cpu resources and the fact that you are using translation and full system emulation.
so I guess that means QEMU always does full translation instead of just translating the privileged ops? (ala what vmware's innovation back in the day was)
It means that you can run SMP guest on SMP system and use more than one host core for that. You could run SMP guests before, but they were limited to only one host thread.
Here is a paper from last month's CGO2017 conference, explaining the techniques more in detail: http://www.cs.columbia.edu/~cota/pubs/cota_cgo17.pdf