I don’t know how useful they are in scientific computing either, really. They are less precise than normalized numbers… if flushing them makes a difference I think it is a bad algorithm smell.

But that same statement applies to normal values too, right? With normal numbers you might get the oddity of a-b -> a even if b is nonzero, but you don't get the oddity of a-b -> 0 unless the same number is represented, IIUC. A and B might not be bit identical, but they represent the same number if the difference is 0.

One nice thing that subnormals get you is the property that if x-y == 0 then x == y. If you want to guard against division by 0, and your denominator is a difference of two terms, it’s nice to be able to check equality of those terms and know that if they are not equal, then their difference will not be 0.

More generally, subnormals are needed for Sterbenz Lemma to hold everywhere: https://en.wikipedia.org/wiki/Sterbenz_lemma

I don’t know if any bugs contribute to this but this in the intel case but it has been very common historically for subnormal performance to be lower on many processors, and things like the Alpha required you to handle them in software if the COU fired a trap.

Have a look at https://en.wikipedia.org/wiki/Subnormal_number for some context.

It probably means Apple spent the silicon to handle subnormals at full speed in hardware, rather than triggering a slow microcode handler for such numbers.

I don't know who is down voting you. AFAIK IEEE 754:2008 does require support for subnormals. You can optionally have modes that flush them to zero, but you must support subnormals.

I haven't done any work on this stuff since 2019, so my memory may be hazy.

Probably different teams. Plus you can not underestimate the role that momentum plays in semiconductor engineering teams. If some respected person determined that subnormals are either Hard (tm) or not a Real Problem (tm), it will take a long time to correct this mistaken belief. I believe there have been some recent academic papers on FP implementation from the Intel E-Core team, which is a sign that they are a bit more with the times.

larger SIMD ALUs, which also have been around for longer?

They are designed by different teams and have different ways of doing math. You could just as easily say “why are the efficiency cores wasting an extra cycle for each multiplication doing fixups of an uncommon case”.

Fabian Giesen explains in more detail here: https://mastodon.gamedev.place/@rygorous/117277063419144390

If you use -ffast-math when linking an executable but not a shared library, both gcc and clang will link in crtfastmath.o which has the bit of code to set the DAZ/FTZ flags.

Usually IEEE floats have an implied 1 in the front. So for the standard represented numbers, there's some minimum number 1.bbbbbb.. * 2^-N. This allows 1bit more precision than is actually stored.

between any two numbers, there's basically the same epsilon difference, but from the smallest number to zero it's bigger.

A subnormal number breaks that convention, it just becomes 0.bbbbb... * 2^-N. As the numbers get smaller, the relative difference between the numbers gets larger. That also means their precision is smaller than the normal floats.

AFAIK ARM NEON always works in that mode

This was only true for ARMv7 NEON (32-bit). ARMv8 / AArch64 NEON is IEEE compliant.

That depends on how you store it.

Each number can be written in infinitely many ways, for example 12, 1.2E1, and 0.012E3 all are “twelve”

In (binary) IEEE floats, the canonical way to write floats is

  significant × 2^exponent

with 1 ≤ significant < 2. So, “twelve” gets stored as 1.5 × 2³ and not as, for example, 0.375 × 2⁵, 12 × 2⁰ or 96 × 2⁻³.

Float operations normally return numbers satisfying that.

However, in IEEE, the exponent cannot be made arbitrary small. Because of that, some very small numbers cannot be represented that way.

In those cases the standard says operations can return numbers with the value closest to the correct value with a significant less than 1. Those number representations are called subnormals.

8-bit: There is no IEEE 754 standard format.

16-bit: https://en.wikipedia.org/wiki/Half-precision_floating-point_...

Yes, that's a perfect explanation!

(And thankfully, for when I work with small numbers, they are still much larger than that.)

Very interesting, you are right. The IEEE 754 standard defines positive/negative zero as not subnormal numbers.

Mechanically speaking, the two zeros use the subnormal number format, so in that sense they are subnormal (but definitionally they aren't). Also, I guess FPUs treat zero differently from other subnormal numbers, which is why zero doesn't have a performance penalty.

Relevant articles to read: https://stackoverflow.com/questions/73890260/why-is-zero-not... , https://en.wikipedia.org/wiki/Sterbenz_lemma , https://en.wikipedia.org/wiki/Subnormal_number

Binary floating-point numbers are scientific notation except the pieces are all in binary. In proper scientific notation, the only time the digit before the decimal point can be 0 is when the number itself is 0. Since the only other digit in binary notation is 1, there is no need to store the digit before the decimal point, since it's always 1... except now you can't store 0.

This problem is fixed by reserving one of the exponents for the representation of 0. Some of the formats (e.g. VAX floating point) that introduced this implicit-1-bit for the binary format said that every number with this special-0-exponent was a zero. But IEEE 754 introduced the concept of gradual underflow, and says instead that it is a bit string with the implicit digit before the decimal point as a 0 instead of 1.

Putting it differently and more succinctly: a subnormal number is a number that has fewer digits of precision than is normally implied by the format. Which numbers are subnormal numbers is entirely dependent on the floating-point format.

That's what I mean though- in the Core 2 Duo vs K8 / Athlon days, Intel was much slower for denormals and subnormals than AMD. I'm not sure why but I thought this was common knowledge.

This is true on most hardware. Running ftz on H100s or B200 gives a free 10-20% boost for GEMM-epilogue workload

And yet floating point math in general is non-deterministic across different CPUs. IEEE 754 was not good enough, so it's a valid question.

It used to be quite normal to add a low level random signal to inputs when writing DSP code so as to avoid dropping into subnormal territory. Careful analysis of the algorithm would identify any points where this was also necessary (e.g. feedback paths when running delays).

Obviously those lucky/unlucky enough to be writing 56k fixed precision code wouldn't have this concern, but other ones instead :)

I think flush to zero is probably the preferred strategy these days.